1. Field of the Invention
This invention relates to an electrically rewritable and nonvolatile semiconductor memory device and the method of operating the same. It is further related to a nonvolatile semiconductor memory device, such as NAND cell type, NOR cell type, DINOR cell type, and AND cell type EEPROM.
2. Description of the Related Art
An electrically erasable and programmable EEPROM, such as a NAND cell-type EEPROM that configures a NAND cell with a plurality of serially connected memory cells, has been known as one of semiconductor memory devices. A memory cell in the NAND cell-type EEPROM has a FETMOS structure with a charge storage layer (floating gate) and a control gate stacked on a semiconductor substrate. The memory cell stores data “0” or “1” depending on the amount of charge accumulated in the floating gate.
For market expansion of a semiconductor memory device, high integration of a semiconductor memory device and the reduction in cost are required. Data programming of an NAND type flash memory is performed sequentially from the memory cell which is most separated from a bit line. Under the data programming, 0V (“0” data programming) or supply voltage Vcc (“1” data programming) is applied to a bit line according to program data.
Vcc is given to the selected bit-line side selection gate line.
When a bit line is 0V, at the connected selected NAND cell, the potential is fixed to 0V through a selection gate transistor.
When a bit line is biased at Vcc, selected NAND cell is charged to Vcc−Vtsg through a selection gate transistor. Here, Vtsg is the threshold voltage of a selection gate transistor. Then, the control gate line of the selected NAND cell is set to Vpp (about 20V, program voltage) from 0V. Further, the control gate line of non-selected memory cell in the selected NAND cell is set to Vmg (about 10V: middle voltage) from 0V. Here, in selected NAND cell, when the bit line was 0V, the channel part of the NAND cell is fixed to 0V.
A potential difference (about 20V) occurs between the gate (Vpp potential) and channel part (0V) of the selected NAND cell, and electron injection occurs from the channel part to the floating gate. Then the threshold voltage of the selected NAND cell shifts in the positive direction. This state is data “0.”
On the other hand, when the bit line is biased at Vcc, the channel part of the selected NAND cell is in a floating state. For this reason, with a voltage rise from 0 V to Vpp or Vmg of the control gate line of the selected NAND cell, and since the control gate line is under the influence of capacitive coupling between channel parts, a channel potential goes up from Vcc−Vtsg to Vmch (about 8V), while the potential of a channel part had maintained the floating state.
At this time, the potential difference between the gate (Vpp potential) of the selected NAND cell and channel parts (Vmch) are comparatively as small as about 12V. So an electron injection does not occur. Therefore, Vth (threshold voltage) of the selected NAND cell does not change but is maintained at the negative state. This state is data “1.”
Data erasure of an NAND type flash memory is simultaneously performed to all the NAND cells in the selected NAND cell block. First, all control gates in the selected NAND cell block are set to 0V. The control gates, all the selection gates in non-selected NAND cell blocks, the bit line, and the source line, are set floating. A high voltage of about 20V is biased to the p type well. Thereby, in all of the NAND cells in the selected NAND cell block, the electrons in the floating gate are emitted to the p type well, and the threshold voltage is shifted in the negative direction. Thus, in an NAND cell type flash memory, data erasure will be performed per block.